Speeding-Up Radio-Frequency Integrated Circuit Sizing with Neural Networks

In this book, innovative research using artificial neural networks (ANNs) is conducted to automate the sizing task of RF IC design, which is used in two different steps of the automatic design process. The advances in telecommunications, such as the 5th generation broadband or 5G for short, open doors to advances in areas such as health care, education, resource management, transportation, agriculture and many other areas. Consequently, there is high pressure in today's market for significant communication rates, extensive bandwidths and ultralow-power consumption. This is where radiofrequency (RF) integrated circuits (ICs) come in hand, playing a crucial role. This demand stresses out the problem which resides in the remarkable difficulty of RF IC design in deep nanometric integration technologies due to their high complexity and stringent performances. Given the economic pressure for high quality yet cheap electronics and challenging time-to-market constraints, there is an urgent need for electronic design automation (EDA) tools to increase the RF designers' productivity and improve the quality of resulting ICs. In the last years, the automatic sizing of RF IC blocks in deep nanometer technologies has moved toward process, voltage and temperature (PVT)-inclusive optimizations to ensure their robustness. Each sizing solution is exhaustively simulated in a set of PVT corners, thus pushing modern workstations' capabilities to their limits.
Standard ANNs applications usually exploit the model's capability of describing a complex, harder to describe, relation between input and target data. For that purpose, ANNs are a mechanism to bypass the process of describing the complex underlying relations between data by feeding it a significant number of previously acquired input/output data pairs that the model attempts to copy. Here, and firstly, the ANNs disrupt from the most recent trials of replacing the simulator in the simulation-based sizing with a machine/deep learning model, by proposing two different ANNs, the first classifies the convergence of the circuit for nominal and PVT corners, and the second predicts the oscillating frequencies for each case. The convergence classifier (CCANN) and frequency guess predictor (FGPANN) are seamlessly integrated into the simulation-based sizing loop, accelerating the overall optimization process. Secondly, a PVT regressor that inputs the circuit's sizing and the nominal performances to estimate the PVT corner performances via multiple parallel artificial neural networks is proposed. Two control phases prevent the optimization process from being misled by inaccurate performance estimates. As such, this book details the optimal description of the input/output data relation that should be fulfilled. The developed description is mainly reflected in two of the system's characteristics, the shape of the input data and its incorporation in the sizing optimization loop. An optimal description of these components should be such that the model should produce output data that fulfills the desired relation for the given training data once fully trained. Additionally, the model should be capable of efficiently generalizing the acquired knowledge in newer examples, i.e., never-seen input circuit topologies.

António Gusmão received Licenciado and M.Sc. degrees in Electrical and Computer Engineering from Instituto Superior Técnico, University of Lisbon, Portugal, in 2017 and 2019, respectively. He is with Instituto de Telecomunicações in Lisbon since 2019, where he is now doing his Ph.D. His research interests are in EDA using machine learning approaches and graph theory.
Nuno Horta (S'89-M'97-SM'11) received the Licenciado, M.Sc., Ph.D. and Habilitation degrees in Electrical and Computer Engineer from Instituto Superior Técnico (IST), University of Lisbon, Portugal, in 1989, 1992, 1997 and 2014, respectively. In March 1998, he joined the IST Electrical and Computer Engineering Department where he is currently Associate Professor with Habilitation. Since 1998, he is, also, with Instituto de Telecomunicações, where he is Head of the Integrated Circuits Group. He has supervised more than 100 post-graduation works between M.Sc. and Ph.D. theses. He has authored or co-authored more than 150 publications as books, book chapters, international journals papers and conferences papers. He has also participated as Researcher or Coordinator in several National and European R&D projects. He was General Chair of AACD 2014, PRIME 2016 and SMACD 2016 and was Member of the organizing and technical program committees of several other conferences, e.g., IEEE ISCAS, IEEE LASCAS, DATE, NGCAS, etc. He is Associated Editor of Integration, The VLSI Journal, from Elsevier, and usually acts as Reviewer of several prestigious publications, e.g., IEEE TCAD, IEEE TEC, IEEE TCAS, ESWA, ASC, etc. His research interests are mainly in analog and mixed-signal IC design, analog IC design automation, soft computing and data science.
Nuno Lourenço received Licenciado, M.Sc. and Ph.D. degrees in Electrical and Computer Engineering from Instituto Superior Técnico, University of Lisbon, Portugal 2005, 2007 and 2014. He was also Invited Assistant Professor in the Department of Electrical and Computer Engineering at IST-UL from 2015 to 2019, where he was distinguished with two 'IST Outstanding Teaching Awards.' He has been with Instituto de Telecomunicações in Lisbon since 2005, where he is Researcher and Invited Assistant Professor in the Department of Informatics at the University of Évora since 2021. He has authored, co-authored and supervised over 80 international scientific publications, including two patents, seven books, three book chapters, 23 international journals and 47 conference papers, and is/was a supervisor in 2 Ph.D. thesis and 8 M.Sc. dissertations. He is/was involved in the Organizing Committee of several International Conferences such as IEEE ISCAS'15, PRIME'16-21 or SMACD'16-21. He is/was Publication Co-chair of the International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design 2016, 2017, 2019 and 2021 and of the Conference on Ph.D. Research in Microelectronics and Electronics (PRIME) 2016, 2019 and 2021 which was technically sponsored by IEEE, IEEE CEDA and IEEE CAS societies. He is General Chair of SMACD 2022. He has received 12 Scientific Awards and Distinctions, including several 'best paper awards,' the 'Best EDA tool' from SMACD'15 competition and the '2010 IET DesignVision Award in the category of Semiconductor IP.' He has participated in several scientific projects with national and international universities and companies, and he is Principal Investigator of the ongoing internal HAICAS project funded by IT. His current research interests include AMS/RF IC design, Evolutionary Computation and Machine Learning applied to Electronic Design Automation and Applied Artificial Intelligence.
Ricardo Martins received the B.Sc., M.Sc. and Ph.D. degrees in Electrical and Computer Engineering from Instituto Superior Técnico - University of Lisbon (IST-UL), Portugal, in 2011, 2012 and 2015, respectively. He is with Instituto de Telecomunicações since 2011 developing tools for electronic design automation, where he now holds a postdoctoral research position. He is also Invited Assistant Professor in the Department of Electrical and Computer Engineering at IST-UL. He has authored or co-authored about 50 publications, including books, book chapters, international journals and conferences papers. His current research interests include: electronic design automation tools for analog, mixed-signal and radiofrequency integrated circuits, deep nanometer integration technologies, soft computing, machine learning and deep learning.