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Physical Design and Mask Synthesis for Directed Self-Assembly Lithography
von: Seongbo Shim, Youngsoo Shin
Springer-Verlag, 2018
ISBN: 9783319762944 , 144 Seiten
Format: PDF, Online Lesen
Kopierschutz: Wasserzeichen
Preis: 96,29 EUR
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Preface
7
Contents
9
Acronyms
12
1 Introduction
14
1.1 Optical Lithography
14
1.2 Next Generation Lithography Technologies
17
1.2.1 Extreme Ultraviolet Lithography (EUVL)
17
1.2.2 Electron Beam Lithography (EBL)
18
1.2.3 Nanoimprint Lithography (NIL)
19
1.3 Directed Self-Assembly Lithography (DSAL)
20
1.4 Overview of the Book
22
References
24
Part I Physical Design Optimizations
26
2 DSAL Manufacturability
27
2.1 DSA Defect
27
2.1.1 DSAL for IC Design and Fabrication
27
2.1.2 Lithography-Induced DSA Defect
29
2.2 DSA Defect Probability
30
2.2.1 Definition
30
2.2.2 Defect Probability Computation
32
2.3 Experimental Observations
33
2.4 Summary
35
References
35
3 Placement Optimization for DSAL
37
3.1 Introduction
37
3.2 Defect Probability of Cell Pair
39
3.3 Post-Placement Optimization
40
3.3.1 Cell Flipping
40
3.3.2 Cell Swapping and Flipping
42
3.4 Automatic Placement
43
3.4.1 Implementation of Placer
43
3.4.2 Considerations on Analytical Placer
46
3.5 Experiments
47
3.6 Summary
50
References
50
4 Post-Placement Optimization for MP-DSAL Compliant Layout
52
4.1 Introduction
52
4.2 MP-DSAL Decomposition
54
4.3 Post-Placement Optimization
56
4.3.1 MP-DSAL Decomposition of Standard Cells
56
4.3.2 Placement Optimization for Cell Row
56
4.3.3 Considerations of Interrow Conflict
58
4.4 Experiments
59
4.5 Summary
60
References
61
5 Redundant Via Insertion for DSAL
62
5.1 Introduction
62
5.2 Preliminaries
63
5.2.1 Defect Probability of Via Cluster
63
5.2.2 Basic Redundant Via Insertion
65
5.3 DSAL Redundant Via Insertion Algorithm
65
5.3.1 Graph Modeling
66
5.3.2 Heuristic Insertion Algorithm
67
5.4 Experiments
68
5.5 Summary
71
References
72
6 Redundant Via Insertion for MP-DSAL
73
6.1 Introduction
73
6.2 Simultaneous Optimization of Redundant Via and Via Cluster
75
6.2.1 ILP Formulation
75
6.2.2 Graph-Based Heuristic
77
6.3 Experiments
79
6.4 Summary
82
References
82
Part II Mask Synthesis and Optimizations
84
7 DSAL Mask Synthesis
85
7.1 Introduction
85
7.2 Inverse DSA
86
7.2.1 Numerical Results
90
7.3 Inverse Lithography
91
7.3.1 Approximation of Cost Gradient
93
7.3.2 Evaluation
95
7.4 Mask Design with Process Variations
96
7.4.1 Inverse DSA and Inverse Lithography
96
7.4.2 Insertion of DSA-Aware Assist Feature
97
7.4.3 Assessment
98
7.5 Summary
99
References
99
8 Verification of Guide Patterns
101
8.1 Introduction
101
8.2 Test GPs
103
8.2.1 Preparation of GPs
103
8.2.2 Evaluation of GP Coverage
106
8.3 Preparing a GP Using Geometric Parameters
106
8.3.1 Geometric Parameters
106
8.3.2 Principal Component Analysis
110
8.3.3 Experimental Observations
111
8.4 Constructing a Verification Function
113
8.5 Experimental Assessment
115
8.5.1 Choice of Parameters
116
8.5.2 Parameter Reduction
117
8.5.3 Comparison of GP Verification Methods
119
8.5.4 A Global Verification Function
120
8.6 Conclusions
121
References
122
9 Cut Optimization
124
9.1 Introduction
124
9.2 Preliminaries
126
9.2.1 Critical Cut Distances in MP-DSAL
126
9.2.2 Wire Extension: Impact on Circuit Timing
127
9.3 MP-DSAL Cut Optimization
128
9.3.1 ILP Formulation
128
9.3.2 Heuristic Algorithm
130
9.4 Experiments
133
9.5 Conclusion
135
References
136
10 Summary of The Book
138
References
140
Index
141